Showing 3 results for Random Number Generator
G. Morankar,
Volume 17, Issue 3 (9-2021)
Abstract
Tremendous developments in integrated circuit technology, wireless communication systems, and personal assistant devices have fuelled growth of Internet of Things (IoT) applications and smart cards. The security of these devices completely depends upon the generation of random and unpredictable digital data streams through random number generator. Low quality, low throughput, and high processing time are observed in software-based pseudo-random number generator due to interrelated data or programs and serial execution of codes respectively. In this paper, FPGA implementation of low power true random number generator through ring oscillator for IoT applications and smart cards is presented. Ring oscillators based on higher jitter and sampling techniques were exploited to present true random number generator. Further statistical parameters of the generated data streams are enhanced through feedback mechanism and post-processing technique. The presented true random number generator technique does not depend on the characteristics of a particular FPGA. The presented technique consumes low power, requires low hardware footprints and passes the entire National Institute of Standards & Technology (NIST) 800-22 statistical test suite. The presented low power and area true random number generator with enhanced security through post-processing unit may be applied for encryption/decryption of data in IoT and smart cards.
Bhagyashree Ingle, Milind Nemade,
Volume 22, Issue 0 (3-2026)
Abstract
Computing paradigm has perceived a logical shift from CPU towards application specific GPU, FPGA, CPLD due to slow down of Moore’s Law, operating system overheads, serial data processing, memory management, power efficiency and speed. The performance increase of general-purpose CPUs & GPUs is unable to match with the advances in peripheral interfaces, reconfigurable logic deployed in FPGAs provides several exceptional properties that may be able to deliver desired performance. FPGA based digital circuits provide an intermediate arrangement between ASIC and CPU with regards to through-put, latency, portability and design time. True random number generators (TRNG) are expensive, low bandwidth and speed, non-compatible with FPGA or heterogenous architectures. Therefore, design and development of alternative and affordable random-number generators is focused by several researchers. TRNG design in FPGAs is more challenging because it must meet low power and area, high speed and throughput requirements without comprising the statistical quality of the desired results for intended applications. In this paper, an attempt has been made to highlight emerging techniques and challenges associated with FPGA implementation of random number generator. Furthermore, forthcoming techniques with the use of heterogeneous computation using FPGA and python productive multiprocessor system on chip (MPSoC) architecture for generation of random numbers are discussed.
Arash Kosari,
Volume 22, Issue 3 (9-2026)
Abstract
Satellite communications are the invisible backbone of our connected world, supporting everything from daily internet access to critical military missions. Yet, beneath their importance lies a hidden vulnerability: the physical layer remains exposed to increasingly sophisticated cyber threats. In this paper, we explore how quantum technologies could be weaponized against these systems and how they might be defended. We present an integrated attack model that brings together Quantum Support Vector Machines (QSVM) for highly precise signal prediction and Quantum Random Number Generators (QRNG) for stealthy noise injection. Using realistic simulations on Qiskit, GNU Radio, and MATLAB, we show that such an attack can succeed 85% of the time, with only a 15% chance of being detected, while causing a 30% rise in bit errors. These results underline the disruptive potential of quantum-enhanced adversaries. To counter this, we propose a layered defense strategy combining post-quantum cryptography, machine learning–driven intrusion detection, adaptive signal processing, and hardware safeguards. Our findings not only reveal the scale of the challenge but also offer a roadmap toward securing future satellite networks in the quantum era.
